1. Field of the Invention
The present invention relates to a semiconductor device and a technique for producing the same, and particularly relates to a silicon carbide semiconductor device constituted by a plurality of power semiconductor devices using a silicon carbide substrate and a technique which is effective by being applied to the production thereof.
2. Background Art
As a power metal insulator semiconductor field effect transistor (MISFET), which is one of the power semiconductor devices, a power MISFET using a silicon (Si) substrate (hereinafter referred to as “Si power MISFET”) was most commonly used in the past.
However, a power MISFET using a silicon carbide (SiC) substrate (hereinafter referred to as “SiC substrate”) (hereinafter referred to as “SiC power MISFET”) can increase pressure resistance and reduce loss as compared with a Si power MISFET. Therefore, a SiC power MISFET has been attracting attention particularly in the field of technology.
A SiC power MISFET can decrease an on-resistance as compared with a Si power MISFET in the case where the pressure resistance is equivalent. This is attributed to the fact that silicon carbide (SiC) has a high dielectric breakdown field strength, which is about 7 times as high as that of silicone (Si), and therefore the thickness of an epitaxial layer serving as a drift layer can be decreased. However, in consideration of the original property which should be obtained from silicon carbide (SiC), a sufficient property has not yet to be obtained, and from the viewpoint of highly efficient utilization of energy, a further reduction in on-resistance has been demanded.
One problem to be solved with respect to the on-resistance of a SiC power MISFET is a low channel mobility, which is a problem specific to a SiC power MISFET. In a parasitic resistance component of a SIC power MISFET having a DMOS (Double diffused Metal Oxide Semiconductor) structure, a channel resistance component has the highest proportion, and the channel mobility of a Si power MISFET is, for example, about 300 cm2/Vs, however, the channel mobility of a SiC power MISFET is about several square centimeters per volt second, which is extremely low.
One of the causes of this low channel mobility is considered to be, for example, as described in V. V. Afanasev et al., “Intrinsic SiC/SiO2 Interface States”, Physica status solidi (a) 162, 321 (1997) (NPL 1), an effect of an interface state at an interface between a SiC substrate and a gate insulating film or an effect of carbon (C) present at an interface between a SiC substrate and a silicon oxide (SiO2) film when a surface of the SiC substrate is oxidized. Such a scattering factor scatters a carrier to deteriorate the channel mobility.
As a method for suppressing the deterioration of the channel mobility, for example, as described in S. Harada et al “High Channel Mobility in Normally-off 4H—SiC Buried Channel MOSFETs”, IEEE Electron Device Letters 22, 272 (2001) (NPL 2), there is a method of using an embedded channel to form a channel at a position deeper than such a scattering factor present at an interface between a SiC substrate and a gate insulating film. By disposing the channel spaced apart from such a scattering factor, the improvement of the channel mobility can be expected.
However, in the case of using an embedded channel, since a distance between the channel and the gate electrode is increased, it becomes difficult for a gate voltage to influence the channel. Therefore, a threshold voltage (Vth) of a SiC power MISFET in which an embedded channel is used is lower than that of a SiC power MISFET in which an embedded channel is not used. Due to this, a SiC power MISFET in which an embedded channel is used exhibits normally-on characteristics. Further, even if it is a normally-off type SiC power MISFET, it has a problem of low threshold voltage, for example, a high threshold voltage which is sufficient so as not to cause malfunction cannot be obtained, etc.
Accordingly, a technique for increasing a threshold voltage becomes important. For example, JP-A-2001-94097 (PTL 1) discloses a method for obtaining normally-off characteristics by forming a p-type channel layer in addition to an n+-type embedded channel layer.
Further, for example, JP-A-2007-13058 (PTL 2) discloses a method for obtaining normally-off characteristics by forming a p-type channel layer in addition to an n-type embedded channel layer not only in a SiC power MOSFET having a DMOS structure, but also in a SiC power MOSFET having a trench structure. By forming a SiC power MOSFET having a trench structure in this manner, the channel mobilityis increased to 100 cm2/Vs, and therefore, the channel mobility can be increased as compared with a SiC power MOSFET having a DMOS structure.
Further, in a SiC power MISFET having a DMOS structure, in the case where a channel is formed by performing light exposure twice, i.e., by performing light exposure for forming a JFET (Junction Field Effect Transistor) region and light exposure for forming a source region, a problem arises that in the channels on both sides of the JFET region, due to misalignment, the length of one channel is shorter than that of the other channel. In the case where a channel length is decreased, this problem cannot be ignored, and for example, a shift of the threshold voltage or kink in the drain current-gate voltage characteristics is liable to occur.
However, in the case where a channel is formed by self-aligning, the above-described problem of misalignment caused by performing light exposure twice can be avoided, and with respect to a reduction in channel resistance, a reduction in channel length synonymous with improvement of channel mobility can be expected.
However, a SiC power MISFET having a DMOS structure still has various technical problems as described below even if an embedded channel and a p-type channel are used in combination, and a short channel is formed by self-aligning.
First, a problem in the case of using an embedded channel and a p-type channel in combination will be described.
An embedded channel is a technique in which a channel is formed at a position deeper than an interface between a SiC substrate and a gate insulating film by forming a p−-type body layer including a region serving as a channel on a SiC substrate, and thereafter implanting an n-type impurity into a surface layer portion of the p−-type body layer. In general, a p-type impurity, for example, an aluminum atom (Al) or a boron atom (B) is implanted into a SiC substrate, thereby forming a p−-type body layer. Thereafter, an n-type impurity, for example, a nitrogen atom (N) or a phosphorus atom (P) is counter-implanted into a surface layer portion of the p−-type body layer, thereby forming a counter layer exhibiting p−-type, intrinsic, or n−-type conductivity in the surface layer portion of the p−-type body layer, whereby an embedded channel is formed.
By using this embedded channel and a p-type channel in combination, the channel mobility is improved and also a decrease in threshold voltage can be suppressed.
On the other hand, in a SiC power MISFET, a gate voltage is higher than a drain voltage in view of the nature of its operation, and therefore, an electric field in an end portion of a source region is increased. Due to this, a gate insulating film in an end portion of the source region is liable to be deteriorated. The deterioration of the gate insulating film in an end portion of the source region is liable to cause a variation in threshold voltage as compared with the other portions, and therefore, this generation of a high electric field in an end portion of a source region is one of the problems of a SiC power MISFET. In addition, when an embedded channel and a p-type channel are used in combination, the p-type channel having a high impurity concentration is in contact with the source region, and therefore, an electric field in an end portion of the source region is further increased, as a result, deterioration of the gate insulating film in an end portion of the source region becomes more prominent.
Next, a problem in the case of forming a short channel by self-aligning will be described.
As described above, the formation of a short channel by self-aligning has an advantage that a problem of misalignment caused by performing light exposure twice can be avoided in addition to an advantage that it is useful as a method for compensating the problem of low channel mobility. However, if the length of the channel is extremely decreased, a negative effect that the threshold voltage is decreased occurs.